In an SRAM, Refresh operation to retain data is not performed, therefore, the SRAM has a higher operation speed as comparing with a DRAM (Dynamic Random Access Memory). From view point of the operation speed, SRAM is applied to a cache memory or the like. Conventionally, an SRAM memory cell is composed of six transistors, that is, two road P-channel MOS transistors, two driver N-channel MOS transistors and two transfer N-channel MOS transistors. The SRAM memory cell has two inverters and each inverter is composed of one of the road P-channel MOS transistors and one of the driver N-channel MOS transistors (for example, Japanese Patent Publication (Kokai) No. P2004-273972, P11, FIG. 2).
Recently, high packing density in memory capacity and low voltage in power supply have been progressed in SRAM technology, which lead to cause deteriorating stability of storing data. As a method for improvement of the stability of storing data, increasing a number of transistors above six transistors in the SRAM cell have been proposed (for example, ISSCC (International Solid-State Circuits Conference), No. 34.4, 2006).
However, the method mentioned above has several problems. For example, as a number of elements in the SRAM cell is larger than that in the DRAM cell, an area in the SRAM cell is larger than that in a DRAM cell only having one transistor and one capacitor. Further, larger cell area lead to increasing a cost of SRAM memory product.